Arm Cortex processor behaviors Community

Event Information

Share this event

Date and Time




Refund Policy

Refund Policy

Contact the organiser to request a refund.

Event description



  • Introductory knowledge of either the A, R, or M profile of the Arm architecture.


The course is aimed at Hardware Engineers needing an understanding processor signal behaviors. The course will also benefit software and implementation engineers.

Delivery Method:

  • Online


  • 1 hour


  1. Introduction

    • Topic overview

    • Simple Sequential Model

  2. Instruction fetching optimizations

    • Intro to instruction fetching optimizations

    • Branch prediction overview

    • Branch prediction method (return stack)

    • Branch prediction method (conditional branch prediction)

    • Effects of branch prediction

  3. Data processing optimizations

    • Data processing optimizations - overview
    • Multiple execution pipelines
    • Speculative execution
    • Register dependencies
    • Cortex-A, R, and M interrupt behaviors
  4. Data memory access optimizations

    • Data memory access optimizations - overview

    • Caching (cache eviction)

    • Caching (cache pre-fetching performance

    • Caching (cache maintenance - multi-caching)

    • Merging

    • Re-ordering overview

    • Re-ordering commands

    • ISB and DSB example

    • Barriers and speculative access

  5. Summary

    • Cortex-A summary

    • Cortex-R summary

    • Cortex-M summary

Language: This course is presented in English.

Delivery Method: Bitesized video content

By booking this training course you accept our Terms and Conditions.

You will have 3 months access to this community.

Share with friends

Date and Time



Refund Policy

Contact the organiser to request a refund.

Save This Event

Event Saved