Arm Cortex processor behaviors Community 

Arm is at the heart of the world’s most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.Arm provides training on a wide range of Arm technology topics, written and delivered by the world’s most experienced Arm technology trainers. With face-to-face and online options available, Arm Training is flexible too.

<H3>Prerequisites:</H3>
<UL>
<LI>
Introductory knowledge of either the A, R, or M profile of the Arm architecture.
</LI>
</UL>
<H3>Audience:</H3>
The course is aimed at Hardware Engineers needing an understanding processor signal behaviors. The course will also benefit software and implementation engineers.
<H3>Delivery Method:</H3>
<UL>
<LI>Online</LI>
</UL>
<H3>Length:</H3>
<UL>
<LI>1 hour</LI>
</UL>
<H3>Modules:</H3>
<OL>
<LI>
Introduction
<UL>
<LI>
Topic overview
</LI>
<LI>
Simple Sequential Model
</LI>
</UL>
</LI>
<LI>
Instruction fetching optimizations 
<UL>
<LI>
Intro to instruction fetching optimizations
</LI>
<LI>
Branch prediction overview
</LI>
<LI>
Branch prediction method (return stack)
</LI>
<LI>
Branch prediction method (conditional branch prediction)
</LI>
<LI>
Effects of branch prediction
</LI>
</UL>
</LI>
<LI>
Data processing optimizations  
<UL>
<LI>Data processing optimizations - overview</LI>
<LI>Multiple execution pipelines</LI>
<LI>Speculative execution</LI>
<LI>Register dependencies</LI>
<LI>Cortex-A, R, and M interrupt behaviors</LI>
</UL>
</LI>
<LI>
Data memory access optimizations
<UL>
<LI>
Data memory access optimizations - overview
</LI>
<LI>
Caching (cache eviction)
</LI>
<LI>
Caching (cache pre-fetching performance
</LI>
<LI>
Caching (cache maintenance - multi-caching)
</LI>
<LI>
Merging
</LI>
<LI>
Re-ordering overview
</LI>
<LI>
Re-ordering commands
</LI>
<LI>
ISB and DSB example
</LI>
<LI>
Barriers and speculative access
</LI>
</UL>
</LI>
<LI>
Summary
<UL>
<LI>
Cortex-A summary
</LI>
<LI>
Cortex-R summary
</LI>
<LI>
Cortex-M summary
</LI>
</UL>
</LI>
</OL>
Language: This course is presented in English.
Delivery Method: Bitesized video content 
By booking this training course you accept our <A HREF="http://www.arm.com/files/pdf/LES-PRE-20934_ARM_Event_Booking_Terms-EventBrite-v0.8.pdf" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">Terms and Conditions</A>.
You will have 3 months access to this community.

Arm Cortex processor behaviors Community

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