Designing the future: Tackling design challenges through collaboration

Sponsored by IC Resources

TechWorks DESN network aims to support the UK chip design industry by building communities of shared interest. This launch event will define new collaborative groups to address shared challenges and opportunities.

As chip complexity continues to accelerate, designers face growing challenges in architecture design, system scaling & integration and workflow. This hands-on event brings together chip architects, designers and engineers to explore real-world pain points and application trends, sharing lessons learned. The objective is to build ongoing collaboration supporting industry growth.

We will explore three contemporary themes during the event, with a plenary discussion following each one to discuss the topics raised and identify relevant actions and initiatives for DESN to curate going forward.

Speakers

Nigel Toon

AI Entrepreneur & Founder CEO, Graphcore.ai.

Nigel is a leading AI entrepreneur and is the founder and CEO of Graphcore.ai. He sits as a Non-Executive Director on the board of UK Research and Innovation and sat on the UK Prime Minister's Business Council.

He has been recognized with numerous industry awards, being ranked #1 on Business Insider's UK Tech 100 and named as one of the 'Top 100 entrepreneurs in the UK' by the Financial Times.

He was awarded a Doctor of Science degree from the University of Bristol and is the author of the best-selling book How AI Thinks.

Prashant Dubey

Path Finding Researcher, Imec Cambridge UK

Prashant Dubey is a pathfinding researcher at Imec Cambridge UK, where he is engaged in STCO on 2nm nanosheets/forksheets and CFETS. This involves 3D and wafer level integration of TByte scale SRAMs, integrated buck converters for high voltage to low voltage vertical power delivery, back-side clock generation and routing and high-speed interconnects (petabytes/sec), for AI driven HP Compute in Data-Center applications. Prashant received his BE degree from Gorakhpur University, India in 1998 and MS research degree from IIT Delhi, on hyper-coupled ring oscillators. From 1998 to 2012 he worked for STMicroelectronics India as a Senior Design Expert, Analog & RF, where he designed embedded SRAMs and ROMs, memory and SoC DFT, analog and digital integer-N and fractional PLLs and oscillators. From 2012 to 2017 he worked for Synopsys India and led the research on low voltage SRAM architectures in 16-7nm FinFETs on write/read assist. From 2017 to 2018 he worked with Xilinx India on 3D FPGA architectures and in 2018, joined ARM Cambridge UK and then MediaTek UK where he worked on voltage droop mitigation sensors and 5G mmW, sub-100fs integrated jitter PLLs with dead-zone less 1st-order noise-shaped TDC architecture. He has produced, 25 US Patents and 14 IEEE publications.

Rob Dimond

System Architect and Fellow, Arm

Rob is a member of the leadership team for the Architecture and Technology group at Arm where his focus is future technology development for the infrastructure segment (servers & networking).

Prior to Arm, Rob was Chief Hardware Architect at FPGA computing start-up Maxeler. Rob holds degrees in Electronic Engineering and Computer Science from Imperial College, London.