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DVClub - 14 January 2012 (Open Source Verification Tools)

Test and Verification Solutions

Monday, 14 January 2013 from 12:00 to 14:00 (GMT)

DVClub - 14 January 2012 (Open Source Verification...

Ticket Information

Type End Quantity
Bristol Ended Free  
Cambridge Ended Free  
Remote Access Ended Free  
Eindhoven Ended Free  
Grenoble Ended Free  

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Event Details



Open Source Verification Tools


Monday 14 January 2013

from 12.00 to 14.00 at various locations


  • Bristol:  Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP
  • Cambridge:  ARM, 110 Fulbourn Road, Cambridge, CB1 9NJ
  • Eindhoven: Intel, High Tech Campus, Eindhoven 
  • Grenoble:  STMicroelectronics - Polygone Scientifique, 12 Rue Jules Horowitz, Grenoble
  • Remote Access 


Agenda (UK) GMT

11.30   Arrival and Networking

12.00   Mike Bartley (Welcome)

12.05   Wilson Snyder (Veripool)

12.35   Dag Arne Braend (Atmel)

13.00   Maksim Jenihhin (Tallin University of Technology, Estonia) 

13.20   Rich Porter (Design & Verification Engineer)

13.40   Close and Networking

 Agenda details available below for Remote Access, Europe and India

Wilson Snyder (Consulting Engineer, Veripool)

Title:  Verilator and Open-Source Simulation Challenges

Abstract:  Wilson Snyder, the primary author behind Verilator will discuss the recent progress behind Verilator - the fastest open source simulator - and discuss some of the challenges behind open source simulation. 

Biography:  Wilson Snyder is a consulting engineer with Cavium Networks in Marlboro, Massachusetts, USA.  A graduate of Rensselaer, he has held ASIC design and microprocessor architecture positions at Digital Semiconductor, Maker Communications, and Sun Microsystems, and SiCortex.  He makes numerous contributions to public domain engineering tools, such as Verilog-Mode for Emacs and Verilator, available off his website.

As a short taster of what’s to come in January Wilson Snyder has taken the time to give us a Verification Insight into Verilstor and tells us why Verilator was started, the business model, user base and the future for Verilator. Use this link to hear the interview.

Dag Arne Braend (Senior Director Atmel MCU Tools, Atmel)

Title:  Use of microcontroller simulator models in Atmel Studio – and how to make them.

Abstract:  This presentation focuses on how use microcontroller simulator models as a part of the development process for new products, what requirements this places on the models and how to make and integrated them into the development environment.

Biography:  Born in Trondheim Norway 1960 and attached M.Sc. EE, NTH, Trondheim Norway 1984.  

Worked at the department of Physical electronics NTH 1985-1986 as a research assistant

Worket at Universty Hosiptal in Trondheim 1986 with Quality Control of electro medical equipment.

Worked for Metron (Norwegian start-up company later sold to Fluke) developing microcontroller based safety analyzers for medical use 1986-1991

Worked for the Konsgberg group as a project manager 1991-1999 mainly focusing on subsea navigation equipment and oceanographic monitoring

Worked for Oceanor developing the core CPU / OS platform for oceanographic buoys 1999-2000

2000 - present worked as the Director for Atmels MCU Tools Development, including Atmel Studio, programmers, debuggers & referenced designs.  Also responsible for Manufacturing and Logistics.


Maksim Jenihhin (Senior Research Fellow, Tallinn University of Technology, Estonia) 

Title:  zamiaCAD: Shall we dance?

Abstract:  This talk will give an overview of an open-source framework zamiaCAD for hardware design and debug which is based on an open and highly scalable model. 

In recent years software development discipline has made significant advances in the area of program code entry, navigation, analysis and debug which resulted in powerful integrated development environments, e.g. the open-source Eclipse IDE. The existing hardware development environments are lacking this progress and remain awkward. The situation is even worse in the open-source tools domain. At the same time, RTL still remains today the primary abstraction level for hardware design entry and the state-of-the-art design flows need to cope with designs of enormous size. 

zamiaCAD addresses the above mentioned issues and makes hardware design fun. The core features of the framework are: pleasant-to-use design entry, efficient design exploration, scalable front-end, free simulator, debug infrastructure and community support. It can serve as a base for academic research environments and as a practical aid at industry. The presentation will include demos of zamiaCAD application for verification and debug tasks. 

Biography:  Maksim Jenihhin is a senior research fellow at Tallinn University of Technology, ESTONIA.  He received his PhD degree from the same university in 2008. His primary research interests include hardware functional verification and debug as well as manufacturing testing topics and EDA methodologies.  He has co-authored 60 journal and conference papers, supervises 4 PhD students, received the IBM Faculty Award 2011/2012, acts as a PC member for a number of IEEE conferences and journals.



Rich Porter (Design & Verification Engineer)

Title:  "Open Source Tools for Verification"

Abstract:  There has been an explosion in open source tools in the last 10 years, as talented engineers and businesses choose to share their quality software. This is a whirlwind tour of the cream of these tools that are freely available and can make significant improvements in the digital design & verification process.

Biography:  Rich has 20 years of digital design & verification experience in both small start ups and large multinational companies.  He spent the first half of his career creating maintainable and reusable RTL, before transitioning to a verification role. His interests include maximising engineering productivity through the use of leading edge process and tooling.



Additional Agenda Information


Agenda (Remote) BST

12.00   Mike Bartley (Welcome)

12.05   Wilson Snyder (Veripool)

12.35   Dag Arne Braend (Atmel)

13.00   Maksim Jenihhin (Tallin University of Technology, Estonia) 

13.20   Rich Porter (Design & Verification Engineer)

13.40   End of Webinar


Agenda (Europe) CET

12.30   Arrival and Networking

13.00   Mike Bartley (Welcome)

13.05   Wilson Snyder (Veripool)

13.35   Dag Arne Braend (Atmel)

14.00   Maksim Jenihhin (Tallin University of Technology, Estonia) 

14.20   Rich Porter (Design & Verification Engineer)

14.40   Close and Networking


Agenda (India) IST (Remote)

17.30   Mike Bartley (Welcome)

17.35   Wilson Snyder (Veripool)

18.05   Dag Arne Braend (Atmel)

18.30   Maksim Jenihhin (Tallin University of Technology, Estonia) 

18.50   Rich Porter (Design & Verification Engineer)

19.10   End of Webinar




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If you do not consent please contact Sara Horrell ( and request to be excluded.

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