Present a paper, start a discussion, demonstrate how your company is a great place to work on FPGA design.
“A bad workman blames his tool” so the saying goes. So a good workman will praise his tools.
The October meet up of the NMI FPGA Network will share experiences of how design tools and methodologies impact the schedule, solve difficult problems, affect quality, optimise architecture, bridge hardware and software communities.
It will provide a stage for end users (the good workmen) and solutions and service providers (also good workmen) to praise what works well so all can benefit from the knowledge.
Synopsys: Flexible debug and visibility techniques to enhance all FPGA design and deployment cycles
BittWare: FPGA platform development kit enables fast TTM
Mentor Graphics: Staying competitive by evolving your FPGA verification methodologies
Bitvis AS: A game changer for VHDL verification: sdvanced VHDL verification - made simple for anyone
Telexsus: FPGA real-time debug with vastly increased operational capture time - live demo
Cadence: 100M gate designs in FPGAs - fact or fiction?
Altera now part of Intel: Zen and the art of high-speed design Xilinx: Vivado HLx Design Methodology
ITDev: Static code analysis using Blue Pearl software
Who should attend?
You will find this meeting compelling if you are an architect, designer, verification specialist, project manager or engineering manager and you care about tools and methodologies to help do a better job of creating FPGA designs or systems based on FPGAs.
Demonstrate leadership. Support the design community.
Sponsorship and exhibition at NMI events present high quality opportunities to meet prospects, re-engage with customers. A range of options exists with preferential rates for NMI member companies.
Click here for detail: FPGA_Sponsorship_Exhibition_Information.