GPU Offloading Applications using Intel Software

Chris Edsall

This workshop, split over two mornings, will focus on DPC++/OpenMP usage and performance tuning for offloading on to GPUs.

<h3>Dates and Times:</h3><ul><li>Session 1: Tues 9 Nov 09:00 - 12:30 GMT</li><li>Session 2: Wed 10 Nov 09:00 - 12:30 GMT</li></ul><h3>Description:</h3><p>New Intel GPUs and to some extent GPUs from other vendors can be utilized by <a href="https://www.intel.com/content/www/us/en/developer/tools/oneapi/overview.html" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">oneAPI software</a>. Two branches can be taken to offload computation from standard C/C++ and Fortran applications.</p><p>The first choice for C++ application would be the use of <a href="https://www.intel.com/content/www/us/en/developer/tools/oneapi/dpc-compiler.html" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">DPC++</a> , Intel's implementation of  <a href="https://www.khronos.org/sycl/" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">SYCL</a>. GPU code is also C++(with certain limitations) and will be identified by the new LLVM Clang compiler. <a href="https://www.openmp.org/" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">OpenMP offloading </a>is an alternative to that can be also applied to C and Fortran codes. By use of the target directive OpenMP codes can be transformed into GPU offloading codes. Existing <a href="https://www.openacc.org/" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">OpenACC</a> codes may be also ported to the more commonly supported OpenMP standard.</p><p>A short overview of the Intel oneAPI Toolkits will be given. Compiler options are crucial for optimal performance and thus a short introduction to optimization flags will be provided. As coding errors can be hard to find, a correctness checking tool that finds real and potential threading and offloading errors will be introduced. Finally, performance bottlenecks will be discussed and methods to detect them will be introduced. </p><h3>Objective:</h3><p>After attending this workshop, you will have learned:</p><p>• Typical code patterns for applying Dpc++/SYCL code and OpenMP directives for parallelizing and vectorizing loops and regions</p><p>• How to use Intel tools effectively.</p><p>• How to apply the Advisor tool for finding appropriate loops for OpenMP offloading.</p><p>• How to check the correctness and finding potential threading errors.</p><p>• How to perform different types of HPC and threading analysis as well as micro architectural analysis using Vtune.</p><p>• General tuning methodologies, common parallel bottlenecks and how to solve them.</p><p></p><h3>Prerequisites:</h3><ul><li>An Intel DevCloud account. You can<a href="https://www.intel.com/content/www/us/en/forms/idz/devcloud-enrollment/edge-request.html" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer"> <strong>sign up here for free</strong> </a></li><li>Basic understanding of parallel programming paradigms and C/C++ or Fortran programming</li></ul>

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