Eventbrite, and certain approved third parties, use functional, analytical and tracking cookies (or similar technologies) to understand your event preferences and provide you with a customised experience. By closing this banner or by continuing to use Eventbrite, you agree. For more information please review our cookie policy.
Invalid quantity. Please enter a quantity of 1 or more.
The quantity you chose exceeds the quantity available.
Please enter your name.
Please enter an email address.
Please enter a valid email address.
Please enter your message or comments.
Please enter the code as shown on the image.
Please select the date you would like to attend.
Please enter an email address.
Please enter a valid email address in the To: field.
Please enter a subject for your message.
Please enter a message.
You can only send this invitations to 10 email addresses at a time.
$$$$ is not a properly formatted colour. Please use the format #RRGGBB for all colours.
Please limit your message to $$$$ characters. There are currently ££££.
$$$$ is not a valid email address.
Please enter a promotional code.
N/A
Sold Out
Unavailable
Please enter a password with at least 8 characters.
You have exceeded the time limit and your reservation has been released.
The purpose of this time limit is to ensure that registration is available to as many people as possible. We apologise for the inconvenience.
This option is not available anymore. Please choose a different option.
Please read and accept the waiver.
All fields marked with * are required.
Please double check your email address. The email address format does not appear valid.
Please double-check your email address. Your emails do not match.
$$$$ requires a number between ££££ and §§§§
US Zipcodes need to be 5 digits.
Post code may contain no more than 9 letter or number characters.
Please double check your website URL.
All fields marked with * are required.
Your card expiration date is in the past.
Your card CSC needs to be 4 digits.
Please confirm your order: $$$$ You have selected to Pay by Cheque.
Click OK to confirm your order.
Please confirm your order: $$$$ You have selected to Pay at the Door.
Click OK to confirm your order.
Please confirm your order: $$$$ You have selected to Pay upon Receiving an Invoice.
Click OK to confirm your order.
Your card CSC needs to be 3 digits.
Sofort is only available in Germany and Austria.
Boleto Bancario is only available in Brazil.
OXXO is only available in Mexico.
PagoFacil is only available in Argentina.
Rapipago is only available in Argentina.
Please enter a valid IBAN number.
You need to accept to charge your bank account.
Your billing zip code needs to be 5 digits.
Please double check your CEP info. The CEP format should be something like 12345-678.
Please double check your tax identifier.
There was a problem saving your address.
There was a problem saving your card info.
There was a problem saving your personal information.
Please select the date you would like to attend.
McAfee Secure sites help keep you safe from identity theft, card fraud, spyware, spam, viruses and online scams.
Copying Prohibited by Law - McAfee Secure is a Trademark of McAfee, Inc.
Unknown card type.
No card number provided.
card number is in invalid format.
Wrong card type or card number is invalid.
card number has an inappropriate number of digits.
Please enter numbers here.
Please enter an integer value.
Numbers must be less or equal to $$$$
All the required fields have not been filled out. Click OK to proceed without all the required information, or click Cancel to finish entering the missing data.
Job titles must be less than 50 characters.
There is currently an issue with card submission on Safari with iOS7. Please try again with a different browser or device.
Sorry, invalid event registration form.
Sorry, invalid event or database error.
Sorry, quantity must be a positive integer.
Sorry, you did not select a valid ticket.
Sorry, invalid event organiser email address.
Your order was cancelled.
Thank You. Your order has been successfully completed. Your name and email address have been added to the list of event attendees.
Sorry, that option is sold out.
Sorry, that option is no longer available.
Sorry, you entered an invalid quantity. Please enter a quantity of 1 or more next to the type or types of tickets you would like to purchase.
Sorry, you did not select any tickets to purchase. Please enter a quantity of 1 or more next to the type or types of tickets you would like to purchase.
Sorry, there are no tickets left for this event.
The tickets, ticket quantity or date and time you've requested are no longer available, due to previous sales. Please choose a different date, time or number of tickets and place your order again.
Sorry, one or more of the tickets you requested are no longer available for purchase.
Sorry, you need to select the date you want to attend.
Sorry, the promotional code you entered is not valid yet.
Sorry, the promotional code you entered has expired.
Sorry, the promotional code you entered is not valid.
Your session has expired. Try ordering again.
Sorry, your requested ticket quantity exceeds the number provided by your promotional code.
This months meeting will be on the theme of RISC-V, an open Instruction Set Architecture (ISA) which started life at the University of California, Berkeley.
Bringing up cycle-accurate models of RISC-V cores -----------------------------------------------
The openness of the RISC-V ISA has enabled the development of many open-source RISC-V cores with varying capabilities. Choosing an implementation that meets given requirements can be done to some extent by comparing specifications and other attributes of the cores, but any decision must be based on actual testing. Using Verilator to generate cycle-accurate models enables rapid development of testing platforms.
This talk provides a report of our experience bringing up cycle-accurate models of two cores, in particular, RI5CY from the PuLP project, and Clifford Wolf's PicoRV32. For testing, a software ecosystem consisting of a compiler, binary utilities, debugger, and an interface between the model and debugger accompanies the Verilator model.
To compare the cores, we used the GCC test suite and the RISC-V ISA test suite for measuring correctness, and the Bristol/Embecosm Embedded Benchmark Suite (BEEBS) to compare performance. All code and scripts used for the implementation are open-source and can be re-used by others who wish to do similar exercises with other RISC-V cores.
Edward Jones has a background in parsing techniques and works at Embecosm on LLVM and GNU toolchains. He is also involved in research by Embecosm to investigate ways in which the software tool chain can reduce program energy consumption. Edward Jones is a Computer Science graduate of the University of Kent.
FreeBSD/RISC-V and Device Drivers
-------------------------------
The FreeBSD port to RISC-V 64-bit ISA was added in January 2016. FreeBSD is the first operating system that officially supported RISC-V in the main repository. Since its introduction, support has evolved, RISC-V privileged architecture has updated a few times. The platform is maturing making it suitable for general, commercial, research and educational use. The GCC v7.0 target for RISC-V was officially up-streamed and NVIDIA is planning to ship all of their GPUs with RISC-V coprocessor enabled in the future. Several companies have announced the start of RISC-V chip development and many universities are taking RISC-V as a target architecture for doing research. The world first RISC-V microcontroller-class board HiFive1 was released and we are getting closer to the first general purpose board to become available! This talk will describe the current status of FreeBSD/RISC-V, toolchain and supported simulators. The porting process as well as describing the latest changes made to FreeBSD in order to support the latest RISC-V privilege specification (v1.10). This includes enabling by default FDT support and drivers attachment change, SBI interface, compiler flags/built-in definition changes, support for updated BBL boot loader, RISC-V privilege levels, initial pa ge tables build, page table entry flags and other changes. An overview of FreeBSD device drivers subsystem will also be covered describing the device frameworks, buses and kernel-interfaces that exists in FreeBSD (e.g. Newbus, cdevsw, bus_dma, SYSINIT, vt, sound, ifnet, spibus, etc), how to use and configure them and how to debug a device driver. This should answer the question: How to write the device driver for FreeBSD/RISC-V?
Ruslan Bukin is a Research Associate at University of Cambridge Computer Laboratory. He has been a FreeBSD user since 2002 and src committer since 2013. His main interests and contributions to FreeBSD are related to computer architectures support, performance monitoring technologies support, hardware tracing technologies (Intel PT), device drivers, DMA engines and DMA frameworks, hardware security (Intel SGX, CHERI), heterogeneous computing. Ruslan is the lead developer of the FreeBSD/RISC-V project. He obtained a Computer Science degree in 2008 from the Peoples' Friendship University of Russia in Moscow
Talk #3 ------ TBA
Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt.
Closing date for bookings is Tuesday 21st November 2017 at 11:30 pm. No more bookings will be taken after this date.
For overseas delegates who wish to attend the event please note that BCS does not issue invitation letters.
We are all responsible for ensuring technology-led change is safe and positive for everyone in society. At BCS we’re committed to meeting this responsibility under royal charter.
That’s why we set the highest standards of professionalism and best practice in the industry, share knowledge, and develop skills and capability tuned to our evolving digital world.
We’ve been supporting the technology industry since 1957 and our 73,000-strong membership spans 150 countries. Every member actively promotes IT professionalism and we provide them with career development opportunities and bring the community together to address the professional, ethical and economic challenges facing technology today.
Share Open Source SG - RISC-V, RISC-V, RISC-V
Share Tweet