RISC-V fpga Understanding Computer Architecture In-person Workshop-Sep 9th

RVfpga (RISC-V fpga) Understanding Computer Architecture - A Hands-On, In-Person, One-Day-Workshop

Bring RISC-V to your course in computer architecture using RVfpga

This workshop shows how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). Let us empower you to teach next generation computer science, electrical and computer engineering students with hands-on real-world expertise in computer architecture and the RISC-V instruction set architecture.

What is the RVfpga workshop about?

RISC-V is a rapidly growing world-wide movement. It is open source and provides extensions, making it easier to target to various platforms. This RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs that are provided as part of the complete RISC-V FPGA (RVfpga) Course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, commercial SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with this FPGA platform and the software tools, enabling a fast start when you return to your university.

What will you learn?

The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.

Specific topics include:

* Installing tools (which can be done before the workshop)

* Targeting the SweRV EH1 RISC-V core to an FPGA

* Analyzing and modifying the RISC-V-core and memory hierarchy

Workshop Schedule: 9AM to 5PM

Draft Schedule:

- Welcome, Introductions and Set-up

- Introduction to the teaching materials and workshop

>>Break

- Instruction and Hands-On Labs

- Overview of the Imagination University Programme

>> Lunch Break and Networking

- Instruction and Hands-On Labs

- Feedback Forms

>>Break

- How to fit RVfpga into your curriculum, Your next steps, Q&A

*The schedule for the day is subject to change. So that you can plan your travel, we will not start earlier than 9AM and our finish will be 5PM latest.

Materials:

All delegates will be given access to the lecture slides and course notes, programming exercises and solutions as well as example exam questions and answers.

Trainer's information:

Sarah L. Harris is an Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. She earned her M.S. and Ph.D. at Stanford University. Before joining UNLV in 2014, she was a faculty member at Harvey Mudd College from 2004-2014. She has also worked at Hewlett Packard, Nvidia, and the Technical University of Darmstadt and has collaborated with other companies including Southwest Research Institute, Intel, and Imagination Technologies. She is the co-author of three popular textbooks: Digital Design and Computer Architecture, 2nd Edition (2007), ARM Edition (2015), and RISC-V Edition (2021). Dr. Harris is also currently leading or co-leading two NSF-funded grants on Smart Cities and on integrating family support in STEM education. Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.

Travelling information

*Location:

- Room: E51-085, Massachusetts Institute of Technology

77 Massachusetts Ave, Cambridge, United States

- Postcode: MA 02139

- Campus Map: http://whereis.mit.edu/?go=E51 [whereis.mit.edu]

*Transportation:

- Airport: Boston Logan International Airport https://www.massport.com/logan-airport/ [massport.com]

- Ground transportation options: Taxi ~45 mins or MBTA train to Kendall/MIT station https://www.mbta.com/stops/place-knncl [mbta.com]

*Hotel:

- where to stay: https://www.mit.edu/visitmit/where-stay/

For more information about the Imagination University Programme and RVfpga CLICK HERE.