RISC-V fpga Understanding Computer Architecture Workshop-Sep 20th

RISC-V fpga Understanding Computer Architecture Workshop-Sep 20th

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On Sale 23 Jul 2022 at 00:00

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University of Alicante

s/n Carretera de San Vicente del Raspeig

03690 San Vicente del Raspeig


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Teaching Computer Architecture? Give us a day of your time, and we will set you up to teach with RISC-V, the fastest growing new ISA

About this event

RVfpga (RISC-V fpga) Understanding Computer Architecture - A Hands-On, In-Person, One-Day-Workshop

Bring RISC-V to your course in computer architecture using RVfpga

This workshop shows how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). Let us empower you to teach next generation computer science, electrical and computer engineering students with hands-on real-world expertise in computer architecture and the RISC-V instruction set architecture.

What is the RVfpga workshop about?

RISC-V is a rapidly growing world-wide movement. It is open source and provides extensions, making it easier to target to various platforms. This RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs that are provided as part of the complete RISC-V FPGA (RVfpga) Course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, commercial SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with this FPGA platform and the software tools, enabling a fast start when you return to your university.

What will you learn?

The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.

Specific topics include:

* Installing tools (which can be done before the workshop)

* Targeting the SweRV EH1 RISC-V core and SoC to an FPGA

* Programming the RISC-V SoC

* Adding more functionality to the RISC-V SoC

* Analyzing and modifying the RISC-V-core and memory hierarchy

Workshop Schedule: 9AM to 5PM

Draft Schedule:

- Welcome, Introductions and Set-up

- Introduction to the teaching materials and workshop


- Instruction and Hands-On Labs

- Overview of the Imagination University Programme

>> Lunch Break and Networking

- Instruction and Hands-On Labs

- Feedback Forms


- How to fit RVfpga into your curriculum, Your next steps, Q&A

*The schedule for the day is subject to change. So that you can plan your travel, we will not start earlier than 9AM and our finish will be 5PM latest.


All delegates will be given access to the lecture slides and course notes, programming exercises and solutions as well as example exam questions and answers.

Trainer's information:

Daniel A. Chaver Martínez obtained a Physics Degree from University of Santiago de Compostela (USC) in 1998 and an Electronic Engineering Degree from University Complutense of Madrid (UCM) in 2000. He developed his PhD from 2000 to 2006 at UCM. He has tought many different courses related to Computer Architecture since 2000. His current research interests include: Architectural Techniques for the Cache and for Non-volatile Memories and OS Scheduling for Asymmetric MultiProcessors. Since 2015, he has been collaborating with Imagination Technologies in the developement of some of their processors and teaching materials.

For more information about the Imagination University Programme and RVfpga CLICK HERE.

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