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Verification Futures Conference (Europe)

Test and Verification Solutions

Thursday, February 5, 2015 from 8:30 AM to 5:30 PM (GMT)

Verification Futures Conference (Europe)

Ticket Information

Type End Quantity
In Person (Reading, UK) Ended Free  
Remote Access Ended Free  

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Event Details

 

Verification Futures

 

Verification Futures is a one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity to user companies to outline their challenges and for the EDA vendors to respond with possible solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe. This year there will be parallel tracks for the first time which will allow us to cover Hardware Verification in general and also verification specifically for FPGA and Embedded System.

 

Overview

When: Thursday 5 February 2015
Where: Reading, UK – Holiday Inn. Wharfedale Road, Winnersh Triangle, Reading, RG41 5TS (M4 J10)
Cost: FREE to attend as a delegate (In Person or Online)
Type: Attend In Person or via Remote Access

 

The Agenda

To review the abstracts for each session, please visit the Verification Futures website.

08:30 Registration, Coffee and Networking
09:25 Welcome: Mike Bartley, Test and Verification Solutions
09:30 Keynote Presentation:
"The Next Three Years"
Cadence Design Systems, Nick Heaton (Distinguished Engineer).
 
10:00 User Panel Session: Our Top Verification Challenges
Panelists:
- Huawei, Martin Dean
- BluWireless, Andy Lunnes
- Imagination Technologies, Colin McKellar
- Wez Davey, DisplayLink (UK) Ltd.
 
10:45 EDA Presentation:
“Verification IP – Trends and Technology for FPGA and ASIC Design Verification”
Mentor Graphics, Adam Rose (VIP Product Marketing Manager)
11:05 Refreshments and Networking
 
  Track #1: Track #2:
11:40 "Can we train our designers to avoid bugs?" Bryan Dickman, ARM Ltd. "Insights into the NMI FPGA Usage Survey of UK and Ireland." NMI, Doug Amos.
"An agile development methodology for FPGA design and verification." Potential Ventures, Chris Higgs.
12:10 "Experience of using SystemC for Design and Verification." BluWireless, Andy Lunnes. "Continuous integration using Jenkins in FPGA Design and verification." Ericsson TV, Alan Fitch.
12:30 "Requirements Driven Verification for Compliance."  TVS, Serrie-Justine Chapman "Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink." Mathworks, Graham Reith. 
13:00 Lunch and Networking
14:15 Keynote Presentation:
- "Navigating efficiently through the Verification Continiuum"
- Synopsys. Joerg Richter (Director R&D)
14:45 EDA Presentation:
- "A View of the Verification Training Market"
- Doulos. John Aynsley (CTO)
15:05 EDA Presentation:
- "A Co-operative Simulation Formal Methodology: Target Verification With Both Barrels."
- OneSpin Solutions. Sergio Marchese
15:25 EDA Presentation:
- FPGA-based Prototyping - Tackling Large Designs Earlier
- S2C Inc. Toshio Nakama (CEO)
15:45 Refreshments and Networking
16:15 Vendor Panel Session: The EDA Response
Panelists:
- Cadence
- Mentor Graphics
- Synopsys
- Doulos
- OneSpin
- S2C Inc.
16:45 Meet the Sponsors in the Exhibition Area
17:15 Event Closes

 

Sponsors

 

 

 

TVS reserves the right to cancel registration at its discretion.

  TVS may share your name and contact details with the sponsors of this event.  

If you do not consent please contact Sara (sara@testandverification.com) and request to be excluded.


Have questions about Verification Futures Conference (Europe)? Contact Test and Verification Solutions
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When & Where


Holiday Inn Reading (M4 J10)
Wharfedale Road
Winnersh Triangle
RG41 5TS Reading
United Kingdom

Thursday, February 5, 2015 from 8:30 AM to 5:30 PM (GMT)


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