Designing the future: Tackling design challenges through collaboration

Sponsored by: Cadence | Synopsys | IC Resources | microTECH global

TechWorks DESN network aims to support the UK chip design industry by building communities of shared interest. This launch event will define new collaborative groups to address shared challenges and opportunities.

As chip complexity continues to accelerate, designers face growing challenges in architecture design, system scaling & integration and workflow. This hands-on event brings together chip architects, designers and engineers to explore real-world pain points and application trends, sharing lessons learned. The objective is to build ongoing collaboration supporting industry growth.

We will explore three contemporary themes during the event, with a plenary discussion following each one to discuss the topics raised and identify relevant actions and initiatives for DESN to curate going forward.

Speakers

Nigel Toon

AI Entrepreneur & Founder CEO, Graphcore.ai.

Nigel is a leading AI entrepreneur and is the founder and CEO of Graphcore.ai. He sits as a Non-Executive Director on the board of UK Research and Innovation and sat on the UK Prime Minister's Business Council.

He has been recognized with numerous industry awards, being ranked #1 on Business Insider's UK Tech 100 and named as one of the 'Top 100 entrepreneurs in the UK' by the Financial Times.

He was awarded a Doctor of Science degree from the University of Bristol and is the author of the best-selling book How AI Thinks.

Prashant Dubey

Path Finding Researcher, Imec Cambridge UK

Prashant Dubey is a pathfinding researcher at Imec Cambridge UK, where he is engaged in STCO on 2nm nanosheets/forksheets and CFETS. This involves 3D and wafer level integration of TByte scale SRAMs, integrated buck converters for high voltage to low voltage vertical power delivery, back-side clock generation and routing and high-speed interconnects (petabytes/sec), for AI driven HP Compute in Data-Center applications. Prashant received his BE degree from Gorakhpur University, India in 1998 and MS research degree from IIT Delhi, on hyper-coupled ring oscillators. From 1998 to 2012 he worked for STMicroelectronics India as a Senior Design Expert, Analog & RF, where he designed embedded SRAMs and ROMs, memory and SoC DFT, analog and digital integer-N and fractional PLLs and oscillators. From 2012 to 2017 he worked for Synopsys India and led the research on low voltage SRAM architectures in 16-7nm FinFETs on write/read assist. From 2017 to 2018 he worked with Xilinx India on 3D FPGA architectures and in 2018, joined ARM Cambridge UK and then MediaTek UK where he worked on voltage droop mitigation sensors and 5G mmW, sub-100fs integrated jitter PLLs with dead-zone less 1st-order noise-shaped TDC architecture. He has produced, 25 US Patents and 14 IEEE publications.

Yiru Zhong

Market Development Specialist, Arm

With more than twenty-five years in the technology sector, Yiru Zhong has led market development for emerging technologies. Yiru’s work spans product strategy, go-to-market design, and partner development, consistently aligning engineering roadmaps with market signals and operational execution. Having experienced through cycles of booms and busts in the last two decades, Yiru brings disciplined judgment about what scales and what does not.

Yiru approaches innovation from the perspective of adoption: who will use it, why it matters, and how value is realised across ecosystems. This orientation enables clear separation of durable demand from transient hype. Drawing on professional and personal experience across Asia and Europe, Yiru bridges diverse customer requirements, regulatory contexts, and supply chains to translate technical potential into commercial outcomes.

John Goodenough

Professor of Microelectronic Systems, University of Sheffield

Inspiring the next generation of talented microelectronic system design engineers, researchers and educators. Driving new programs in research and curriculum that address technology and skills gaps in the Semiconductor Industry. Focus areas on the architecture, integration automation and assurance of secure, power-efficient integrated semiconductor systems.

Previously, experienced Global Technology Executive, Systems and SoC Solutions architect. With broad view across multiple Information Technology, Secure Distributed Embedded Systems, System on Chip (SoC) and Electronic Design Automation.

Dorian Haci

CEO & Co-Founder, MintNeuro

Dr Dorian Haci is an entrepreneur, engineer and researcher with over a decade of experience in academia and industry. As CEO and Co-Founder of MintNeuro, a spinout from Imperial College London, he is pioneering the next generation of neural implants through innovative semiconductor technologies that enable safer, smarter and more scalable brain interfaces. He also serves as an Enterprise Fellow at the Royal Academy of Engineering and a Visiting Researcher at Imperial, where he earned his PhD in microelectronics for implantable medical devices. Under his leadership, MintNeuro has secured multi-million-pound funding from the UK’s NIHR, ARIA and Innovate UK to support R&D collaborations with world-leading research institutes and medical device companies. His work focuses on advancing chip-based solutions for neurological conditions such as epilepsy, Parkinson’s and dementia.

Dr Jeremy Bennett

Founder and Chief Executive, Embecosm

Embecosm was founded in 2008 by Dr Jeremy Bennett, an expert on hardware modeling and embedded software development. Previously Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design where he had been CEO and CTO.

Dr Bennett is author of the popular textbook, “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003) and holds an MA and PhD in Computer Science from Cambridge University.

Mark Zwolinski

Professor, University of Southampton

Mark Zwolinski is a Professor in the School of Electronics and Computer Science, University of Southampton. He has published over 220 journal and conference papers and 3 books. He has supervised 39 PhD students to completion.

His research interests include systems modelling, design for reliability, and heterogeneous computing. He is an Associate Editor of IEEE Transactions on VLSI. He has served on the programme committees of DATE, DAC, CODES+ISSS and ETS. He has also contributed to IEEE standards in test, VHDL and Verilog.

Mark Zwolinski is a Fellow of the IET and BCS, and a senior member of IEEE and ACM. He is a member of the Academic Accreditation Committee of the IET.

Peter Birch

Hardware Lead Engineer, Fractile

Peter Birch is a Hardware Lead Engineer at Fractile, working in the silicon team to deliver industry leading throughput and efficiency for AI inference workloads. Through past experience at VyperCore and Graphcore, he has worked with cutting-edge approaches to design, verification, and infrastructure and advocates for the use of open source tooling and methodologies in commercial ASIC development.