Workshop : Energy Efficient Embedded Machine Vision (E3MV) with FPGAs

Senior Lecturer at Sheffield Hallam University

Dr Kofi Appiah

There is growing momentum for Multi-Processor System on chips (MPSoC) to be used as highly adaptive and efficient accelerators for machine vision and image processing applications. Such systems are composed of multi-architecture solutions and may include a conventional Processing Unit and Field-Programmable Gate Arrays (FPGA) connected via a high-speed BUS. More advanced MPSoCs have Graphics Processing Unit (GPU) and Real-Time Processing Unit like the <A HREF="https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">Xilinx Zynq UltraScale+</A> series. Academics, researchers, PhD students and industrialist interested in the acceleration of machine vision, machine learning and image processing algorithms, are invited to a one-day workshop on “Energy Efficient Embedded Machine Vision” with FPGAs. This workshop is fully funded by the Higher Education Innovation Fellowship (HEIF) Impact fellowships at <A HREF="https://www.shu.ac.uk/research/specialisms/cultural-communication-and-computing-research-institute/research-centres/communication-and-computing-research-centre" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">Sheffield Hallam Universit</A>y (SHU). and supported by Sundance Multiprocessor Technology (<A HREF="http://www.sundance.com" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">Sundance</A>) and Xilinx University Program (<A HREF="https://www.xilinx.com/support/university.html" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">XUP</A>).
<DIV> </DIV>
The day will start with an overview of embedded computer vision systems implemented on general purpose CPUs, GPUs, FPGAs and ASICs. Specific implementation details of real world applications like Automatic Number Plate Recognition (ANPR) and moving object detection on FPGAs will also be presented. Concrete decisions on how to implement <A HREF="https://www.xilinx.com/products/design-tools/embedded-vision-zone.html" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">Deep Learning</A> or Convolutional Neural Networks (CNN) for machine vision systems will also be discussed.
 
The day will end with a hands-on session which will introduce participants to the <A HREF="https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">Xilinx SDx </A>development environment using a typical image processing algorithm as a case study. The hands-on session will target Sundance’s well-engineered platform (<A HREF="http://www.sundance.technology/som-cariers/pc104-boards/emc2-dp/" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">EMC2</A>) with the right combination of parallel and sequential processors, as well as the <A HREF="http://www.tulipp.eu" TARGET="_blank" DATA-MSYS-CLICKTRACK="0" REL="nofollow noopener noreferrer">TULIPP</A> design toolchain which targets for low-power image processing applications. 
 
Program Overview
08:30 – 09:00 Registration, Tea/Coffee 
09:00 – 12:00 Academic Presentations
<UL>
<LI>
            Overview of Embedded Computer Vision Systems - Flemming Christensen, Sundance
</LI>
<LI>
            Automatic Number Plate Recognition (ANPR)  on FPGAs - Dr Xiaojun Zhai University of Derby
</LI>
<LI>
            Moving Object Detection on FPGA - Dr Kofi Appiah Sheffield Hallam University
</LI>
<LI>
            Deep Learning on FPGA (Introduction to Xilinx reVISION stack)  - Peter Hobden, Teledyne e2v
</LI>
</UL>
12:00-13:00 Lunch (Free)
13:00 – 17:00 Hands-on Session
<UL>
<LI>
            System Design on Zynq using Xilinx SDx - Dr Kofi Appiah, SHU
</LI>
<LI>
            Lab session using Tulipp toolchain and Sundance EMC2 hardware - Fatima Kishwar, Sundance
</LI>
</UL>

Sheaf 4301

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Workshop : Energy Efficient Embedded Machine Vision (E3MV) with FPGAs

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